The Blueprints align with Nvidia’s Vera Rubin NVL72 reference architecture and plan to utilize Nvidia’s software stack, including NVIDIA AI Enterprise and Run:AI.

Each 1,152-GPU scalable unit is designed to support gigawatt-scale AI factories, featuring 331TB of HBM4 memory, enhanced memory bandwidth, NVLink, and high-speed networking up to 1.6TB/s using Spectrum-X Ethernet or Quantum-X800 InfiniBand.

The hardware and Blueprints are positioned to support large-scale, liquid-cooled AI deployments and aimed at accelerating time-to-online for AI factories.

Super Micro unveils DCBBS Blueprints for Vera Rubin NVL72 and HGX Rubin NVL8, designed to scale from 5MW to 1GW for end-to-end AI data center deployments.

These new data center solutions are built around Nvidia Vera Rubin platforms, including the Blueprints, to enable scalable, end-to-end AI deployments.

We’re rolling out end-to-end DCBBS Blueprints that cover compute, storage, networking, advanced liquid cooling, power distribution, and site infrastructure, complete with a dedicated deployment team to accelerate AI factory deployments from 5MW up to 1GW.

The Blueprints provide full deployment support from design through on-site integration, enabling turnkey AI factories with scalable capabilities and integrated infrastructure.

Supermicro emphasizes single-vendor accountability by aligning with Nvidia’s Vera Rubin NVL72 reference architecture to reduce integration risk across multiple suppliers.

A public demonstration of Nvidia Vera Rubin and HGX Rubin platforms is planned at Computex in Taipei, running June 2–6, 2026, alongside Nvidia GTC Taipei.

Deployment targets place Vera Rubin-based solutions in the market by the second half of 2026, with demonstrations at major events and alignment to general availability.

The scalable unit is modular, allowing multiple units to scale to meet large-scale AI workload demands and improve performance density and throughput.

The 1,152-GPU unit supports 1,152 Nvidia Rubin GPUs with substantial HBM4 memory, highlighting advancements in memory bandwidth and interconnect efficiency versus prior generations.