Synopsys and TSMC announce certified EDA flows on the TSMC A14 process and report 64G UCIe IP tape-outs on 2nm and 3nm nodes as part of their Open Innovation Platform collaboration.

Co-design paths address power delivery and optics, featuring integrated voltage regulators in a single 3DIC environment and a unified photonic-electronic flow for COUPE to verify optical interconnects within multi-die designs.

The collaboration aims to accelerate AI and high-performance computing by delivering silicon-to-systems co-design capabilities that combine certified EDA solutions and silicon-proven IP with advanced process and packaging innovations.

Agentic AI design flows span Synopsys digital, analog, and multi-die tools, including integrated voltage regulator co-design for CoWoS packaging and a photonic-electronic co-design flow for COUPE co-packaged optics.

A14 certification covers digital and analog flows from implementation to signoff, with ongoing work on analog device routing enablement and an agentic chiplet floorplan co-optimization flow in 3DIC Compiler for heterogeneous multi-die designs on TSMC 3DFabric packaging.

Executives from Synopsys and TSMC emphasize that the collaboration addresses growing AI/HPC demands through integrated solutions and ecosystem collaboration.

On the die-to-die side, Synopsys demonstrated UCIe-A 32G/40G silicon on a TSMC N3P test chip with a CoWoS-S interposer, and completed 64G UCIe IP tape-outs on 2nm and 3nm with embedded DFT for in-system visibility, up to 64 GT/s per UCIe 3.0 spec.

For TSMC’s N2P process, Synopsys reports IP enablement and tape-outs for PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP, and Silicon Lifecycle Management IP, while expanding silicon-proven IP for N3P and N2P and developing IP for 6nm through 3nm compact processes.