Technical specs include a new SP7 socket, 16-channel memory, up to 1.6 TB/s memory bandwidth, and PCIe Gen 6.0 to boost CPU-to-GPU communication for AI accelerators.

Breaking: AMD’s Venice EPYC, the 6th-generation EPYC stack, will be the first server lineup to feature Zen 6, built on TSMC’s 2nm process and ramping in Taiwan with production planned at TSMC’s Arizona facility.

Venice is officially unveiled at AMD’s Advancing AI Event on July 22-23, 2026, with leadership in x86 for standalone workloads highlighted by Mark Papermaster.

The Venice program enters 2nm production to accelerate volume and competitiveness in HPC and AI-centric workloads, with consumer Zen 6 CPUs expected later in 2026 or early 2027.

The coverage situates AMD’s ongoing updates across technologies, consoles, graphics innovations, and PC gaming hardware.

Zen 6 EPYC features emphasize the SP7 socket, 16-channel DDR5 with up to 1.6 TB/s bandwidth, and PCIe 6.0 to support GPUs, AI accelerators, and fast storage.

Venice is positioned to lead traditional standalone x86 workloads as part of AMD’s ongoing x86 leadership strategy, as stated by company executives.

AMD plans to showcase Venice at the Advancing AI event, underscoring its potential impact on data-center workloads and potential Ryzen integration.

Venice is expected to deliver up to 256 Zen 6 cores, up from 192 cores in Zen 5-based EPYC Turin, with independent benchmarks anticipated to show more than 70% gains in performance and efficiency.

The flagship Venice design targets up to 256 Zen 6 cores, a 33% core increase over Turin, aiming for over 70% higher performance and efficiency over Zen 5.

Mainstream Zen 6 consumer CPUs are not expected before year-end 2026, with a probable CES 2027 debut.

Desktop Zen 6 Ryzen processors are anticipated to launch around CES 2027, following the server-focused Venice rollout later in 2026.