Intel’s Diamond Rapids Xeon will be built on an advanced 18A process using a multi-die, Foveros packaging with four compute chiplets and a base die for memory and L3 cache, where the L3 cache is likely on the base die and memory controller placement could be on either the I/O dies or the base dies.

Diamond Rapids is planned for release in 2027, with early spec disclosures at industry events and subsequent briefings to outline performance and licensing implications for hypervisor environments.

Some specifics remain undecided, including clock speed, instruction-per-clock gains, and exact power consumption, which Intel plans to address further at Hot Chips in August 2026.

The platform is targeted at high-demand IaaS and HPC workloads, not mainstream enterprise virtualization or storage servers, aligning with Intel’s 6900P HPC-centric lineup.

Diamond Rapids is expected to feature a very wide memory subsystem with 16 DDR5 channels and potential memory speeds around 8000–9600 MT/s, delivering up to roughly 1.2 TB/s per socket.

The design suggests a centralized memory architecture similar to AMD’s approach, with fewer NUMA nodes if memory controllers are placed on the I/O dies.

At Computex 2026, Intel revealed Diamond Rapids will push core counts to 192—a 50% increase over the prior generation—while also dropping Hyper-Threading (SMT) for these processors.

Although the 192-core configuration marks a major evolution, Intel appears to be accelerating a future reintroduction of SMT under a project code-named Coral Rapids, signaling a partial reversal of the SMT-elimination path.